This invention relates to an up/down counter device operating in synchronism with clock signals.
One of the prior art up/down counter devices is a binary up/down counter TC4516BP manufactured by TOSHIBA. This counter TC 4516BP is configured as briefly explained below. The counter comprises one D-type flip-flop, three JK flip-flops, and three logic circuits for forming JK input signals to the JK flip-flops. Clock signals are coupled with the synchronizing signal input terminals of these flip-flops. The D-type flip-flop is short-circuited between the output terminal Q and the data input terminal to form a binary counter. The output signal Q is used as a count signal at the least significant digit, or of the 0th bit. The JK flip-flops are connected, at the JK input terminals, to the three logic circuits. The output signals of the JK flip-flops are used as the count signals of the 1st to the 3rd bits. Each logic circuit comprises two AND gates and an OR circuit coupled with the outputs of the AND gates. One of two AND gates of the first stage logic circuit receives the reversed signals of the output signal Q0 of the D-type flip-flop, and an up/down mode signal U/D while the other AND gate receives the output signal Q0 and the up/down mode signal U/D. The output signal of the OR gate of the first stage logic circuit inputs to the JK input terminal of the first stage flip-flop. The output signal Q1 of the first stage JK flip-flop, the output signal Q0 of the D-type flip-flop and the up/down mode signal U/D are separately applied to one of the AND gates of the second stage logic circuit. The signal Q1, the signal Q0 and the inverted up/down mode signal U/D are applied to the other AND gate. The output signal of the OR gate of the second stage logic circuit is supplied to the JK input terminal of the second stage JK flip-flop. One of the AND gates of the third stage logic circuit receives the output signal Q2 of the second stage JK flip-flop, the output signal Q1 of the first stage JK flip-flop, the output signal Q0 of the D-type flip-flop and the up/down mode signal U/D. The other AND gate receives the signals Q2, Q1, Q0 and U/D. The output signal from the OR circuit of the third logic circuit is supplied to the JK input terminal of the third stage JK flip-flop.
In the prior up/down counter, thus arranged, as the number of stages of logic circuits for providing input signals for the associated flip-flops becomes larger, the input terminals of the AND gates of the logic circuits increase, one by one, in number. For this reason, in constructing the multi-bit counter, the number of the circuit elements required for the logic circuits exponentially increases with an increase in the number of the logic circuits.